How do I start selecting a Lattice FPGA?

Fix the function first, then the logic and memory budget, then the interfaces and hardened blocks, and finally the package, power and configuration scheme. Those four steps narrow the Lattice catalogue quickly. Start from the device family that matches your function.

ECP5, Certus-NX, MachXO or iCE40: which should I choose?

Choose ECP5 for cost-sensitive bridging and control with SerDes, Certus-NX for hardened PCIe, GigE and DDR3 at low power, MachXO for instant-on non-volatile control and glue logic, and iCE40 for always-on, battery-powered sensing. The decision is function, power and interfaces.

Can BeiLuo help finalize my device choice?

Yes. Send your logic, memory, interface and power requirements and we will propose a shortlist with package options, configuration scheme and stock status, then support design-in and bring-up. Getting the device right saves project time.

What selection mistakes should I avoid?

The usual mistakes are underestimating logic and memory, ignoring I/O standards and power rails, and choosing a package that does not fit the board. Each forces a late change that costs time. Validate the choice with a sample before committing the BOM.

How do I budget MIPI bandwidth on CrossLink-NX?

Multiply the number of active lanes by the per-lane data rate for each camera, sum the streams, and confirm the hardened D-PHY and the pipeline logic can carry the total. Leave margin for blanking and overhead. Download the application note for the full calculation.

How should I route MIPI D-PHY traces?

Keep the differential pairs short, matched within the pair, impedance-controlled and referenced to a solid ground plane, and avoid stubs and layer changes. Follow the Lattice hardware checklist for the package and place the termination and decoupling as recommended. Layout dominates MIPI reliability.

How much logic does an image pipeline need?

It depends on resolution, frame rate and algorithm. A simple format and stream pipeline needs little more than the D-PHY and line buffers, while edge detection, color processing or optical-flow pre-processing consume more fabric and memory. Budget generously and confirm on hardware. View the recommended devices.

Can I support a new sensor later?

Yes. Because the interface is implemented in programmable logic, a new sensor or format can be supported through a firmware update rather than a board change. Confirm the lane count and data rate fit the hardened D-PHY before committing to the new sensor. Ask our FAE team about sensor support.

My iCE40 design draws more current than expected. Where do I start?

Measure the current in each mode first, then check for toggling logic that should be idle, unused clocks left running and I/O pins driving external loads. Most excess current comes from switching activity that the design does not need. Download the troubleshooting guide for the full checklist.

The device wakes too slowly. What could be wrong?

Check whether the design waits for an external clock or reset, or holds a state machine in a long initialization before the always-on function starts. The device itself configures quickly, so a slow wake usually comes from the logic or the configuration scheme. Our FAE team can review your wake sequence.

How do I reduce standby power?

Use the low-power standby mode, clock only the logic that must run, and avoid leaving decoders or counters toggling. Unused I/O should be configured so it does not drive external loads. Measure the result in each mode. Read the iCE40 power guide for the full method.

Can I use an open-source flow and still optimize power?

Yes. The iCE40 families are supported by open-source synthesis, and you can still apply the same power practices such as clock gating and idle-state design. Confirm the final power on hardware regardless of the flow. Ask us about toolchain options.

What is the standout feature of ECP5 SerDes?

ECP5 provides dual-channel SerDes on its UM and UM5G variants at an attractive cost, which lets a compact FPGA implement high-speed serial links to a backplane, optical module or remote device without a separate transceiver chip. The main design care points are the reference clock and the layout.

How do I plan the SerDes reference clock?

Choose a low-jitter oscillator that meets the channel requirement, route it as a controlled differential pair to the dedicated reference pins, and keep it away from noisy supplies. Jitter on the reference clock directly reduces the link margin. Our FAE team can review your clock plan.

How should I route the SerDes pairs?

Use controlled-impedance differential pairs, keep the runs short and matched, reference them to a solid plane and avoid stubs and unnecessary vias. Follow the Lattice hardware checklist for the package and keep the AC coupling and termination as recommended. Layout decides the achievable link margin.

Can I get samples to evaluate?

Yes. We provide ECP5 and ECP5-5G samples for your own link testing, with documentation included and FAE support during bring-up. Request a sample and we will confirm stock and lead time. Validate the link on your board before production.

My MachXO device does not configure on power-up. What should I check?

Confirm the device was programmed successfully, check the power rails and the power-up sequence, and verify the configuration mode pins. A device that programs over JTAG but does not boot often has a supply or mode-pin issue rather than a programming failure. Download the troubleshooting guide for the checklist.

How do I protect my MachXO design from copying?

MachXO devices support configuration security features that prevent the bitstream from being read out. Enable the appropriate security setting in the toolchain, confirm the setting before production programming, and keep a protected copy of the design. Test that an unprotected read is refused. Ask our FAE team about security options.

The device boots but the function is wrong. Why?

Check that the correct bitstream is stored, that the I/O standards and pin assignments match the board, and that any pull-ups or special pins are set as the design expects. A wrong function after a successful boot is usually a bitstream or pin-assignment mismatch. Our FAE team can review your configuration.

Can I update the configuration in the field?

Yes. MachXO devices can be reprogrammed in the field through the supported programming interface, and multi-boot or dual-boot features allow a fallback image if an update fails. Plan the update path and test the fallback before shipping. Ask us about field update design.

Technical Support | Lattice Expertise | BeiLuo

Guides, application notes, troubleshooting and reviews from BeiLuo's FAE team covering Lattice ECP5, Certus-NX, MachXO, iCE40 and CrossLink FPGA families.

Guides 1 Application Notes 1 Troubleshooting 2 Reviews 1

How to Select a Lattice FPGA: ECP5, Certus-NX, MachXO or iCE40

2026-07-24 - Guides - By Zhang Wei

Compare Lattice ECP5, Certus-NX, MachXO and iCE40 FPGA families by logic density, power, I/O and hardened IP to choose the right device for your design.

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CrossLink-NX Application Note: Embedded Vision Interface Design

2026-07-17 - Application Notes - By Chen Hao

Practical guidance for designing MIPI D-PHY camera and display interfaces around Lattice CrossLink-NX FPGAs, including bandwidth budgeting and board layout.

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Troubleshooting and Optimizing Lattice iCE40 Power Designs

2026-07-07 - Troubleshooting - By Chen Hao

A systematic method for diagnosing high current and slow wake in Lattice iCE40 UltraPlus designs, with practical fixes for configuration, clocking and standby power.

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Troubleshooting Lattice MachXO Configuration and Security

2026-06-23 - Troubleshooting - By Zhang Wei

A systematic method for diagnosing Lattice MachXO3 and MachXO2 configuration problems, from programming failures to unexpected boot behavior and security settings.

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Lattice ECP5 SerDes: A Practical Review for Board Designers

2026-06-30 - Reviews - By Wang Lei

A hands-on review of the Lattice ECP5 and ECP5-5G SerDes channels for connectivity and acceleration designs, covering data rates, equalization and layout practice.

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Meet Our FAE Team

Zhang Wei

Senior FAE Engineer, FPGA Applications

FPGADevice ConfigurationTiming Closure

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Chen Hao

FAE Engineer, Embedded Vision and Low Power

Embedded VisionCrossLink-NXLow Power

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Wang Lei

FAE Engineer, High-Speed Interfaces

SerDesECP5Signal Integrity

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